In a transceiver (Transceiver, TRX) circuit of a radio frequency communications system, as shown in FIG. 1, a received RF signal is filtered by a band-pass filter to remove out-of-band interference, and then is amplified by a low noise amplifier (Low Noise Amplifier, LNA) to reduce an impact of noise of a next-level circuit, and then is sent to an input end of a frequency mixer to be mixed with a local oscillator (Local Oscillator, LO) signal. Therefore, a stable LO signal is needed to be used as a reference signal for a transceiver link. The signal is obtained by dividing frequency of an output of a voltage-controlled oscillator (Voltage-Controlled Oscillator, VCO). In order to generate a precise and stable frequency at an output end of the VCO, generally, a phase-locked loop is further used to drive the VCO in a feedback loop, so that an oscillator frequency (or phase) precisely follows an applied reference frequency. With the development of integrated circuit technologies, more and more people tend to use digital logic to implement a frequency division function. Due to features of the digital logic, currently, frequency division ratios of most frequency dividers are integers. This manner limits a frequency range of the LO or has a high requirement on a tuning range of the VCO, which is disadvantageous to implementation of multimode on a same chip. A frequency divider having a non-integer frequency division ratio not only can provide more diverse frequency plans (frequency plan), so that the VCO can cover more communications modes by using a relatively narrow tuning range, but also can stagger an oscillating frequency of the VCO and a high-power harmonic wave of a power amplifier (Power Amplifier, PA), so as to avoid a frequency pulling (frequency pulling) phenomenon.
However, in all existing technical solutions using non-integer frequency division ratios, the frequency division ratio configurability of a frequency divider is generally poor. For example, in the solution of the patent WO2011028157A1, only clock phase arrangement manners in several cases are given, and no dynamic adjustment method is provided. Therefore, the configurability is poor, and a logic circuit is highly complex, which is not suitable for high-frequency working. For another example, in the solution of the patent WO2013048525A1, multiple quadrature signals are input to separately drive corresponding divide-by-5 frequency dividers; pulse signals having a pulse width of one input signal period are generated, and after passing through a narrow pulse generator, the pulse signals are combined together and output as a final signal. In this solution, multiple frequency dividers are completely independent of each other and consume a lot of resources, which is disadvantageous to implementation of low power consumption and low noise. Moreover, multiple frequency dividers start strictly following a required sequence, and therefore, a corresponding start circuit is needed; a sequence of the start circuit is closely related to a frequency division ratio, which does not facilitate to achieve configurability.